Size-filtered multimetal structures

ABSTRACT

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

BACKGROUND

The present disclosure relates to interconnect level structures andparticularly to size-filtered multimetal structures in which metal lineshaving different widths have different metallic compositions, anelectrically programmable fuse (eFuse) employing a different materialfor a metallic fuselink than for a metallic anode and a metalliccathode, and methods of manufacturing the same.

Interconnect level structures, which are also referred to asback-end-of-line (BEOL) interconnect structures, are employed insemiconductor chips to provide horizontal and vertical electricalconnections among various semiconductor devices and/or betweensemiconductor devices and input/output pads that are connected to pinson a packaging substrate. Metal lines provide horizontal electricalconnection, and metal vias provide vertical interconnection. Metal linesand metal vias are embedded in dielectric layers, which are located on asemiconductor substrate on which various semiconductor devices areformed.

Various types of additional metal structures can be formed in thedielectric layers. Such additional metal structures include, but are notlimited to, capacitors, inductors, resistors, and electrical fuses. Anelectrical fuse formed as a metal interconnect structure, which isherein referred to as a metallic electrical fuse, requires much lessdevice area than a metal-silicide-based electrically programmable fuse.

Different metal structures in dielectric layers and/or differentcomponents of a metal structure may require different properties foroptimal performance. For example, a metallic electrical fuse requires ananode structure and a cathode structure that are resistant toelectromigration and an electromigratable fuselink. Thus, integration ofvarious metallic device components within the same level of metalinterconnect structure may require compromise among various deviceperformance requirements.

BRIEF SUMMARY

A size-filtered metal interconnect structure allows formation of metalstructures having different compositions. Trenches having differentwidths are formed in a dielectric material layer. A blocking materiallayer is conformally deposited to completely fill trenches having awidth less than a threshold width. An isotropic etch is performed toremove the blocking material layer in wide trenches, i.e., trencheshaving a width greater than the threshold width, while narrow trenches,i.e., trenches having a width less than the threshold width, remainplugged with remaining portions of the blocking material layer. The widetrenches are filled and planarized with a first metal to form firstmetal structures having a width greater than the critical width. Theremaining portions of the blocking material layer are removed to formcavities, which are filled with a second metal to form second metalstructures having a width less than the critical width.

According to an aspect of the present disclosure, a structure includes:a dielectric layer located on a substrate; a first metallic structureincluding a first metallic portion including a first metallic materialand embedded in the dielectric layer; and a second metallic structureincluding a second metallic portion including a second metallic materialdifferent from the first metallic material and embedded in thedielectric layer.

According to another aspect of the present disclosure, a structureincludes an electrically programmable fuse (eFuse). The eFuse isembedded in a dielectric layer which is located on a substrate andincludes an assembly of a metallic anode, a metallic fuselink, and ametallic cathode. The metallic anode includes a first metallic portionincluding a first metallic material. The metallic cathode includes asecond metallic portion including the first metallic material. Themetallic fuselink contacts the metallic anode and the metallic cathodeand includes a third metallic portion including a second metallicmaterial different from the first metallic material.

According to yet another aspect of the present disclosure, a method offorming a structure is provide, which includes: forming a first trenchhaving a width greater than a threshold distance and a second trenchhaving a width not greater than the threshold distance in a dielectriclayer located on a substrate; forming a blocking material layer in thefirst trench and the second trench; removing the blocking material layerfrom within the first trench while the second trench is filled with aremaining portion of the blocking material layer; filling the firsttrench with a first metallic material and planarizing the first metallicmaterial to form a first metallic structure within the first trench;removing the remaining portion of the blocking material layer selectiveto the dielectric material layer; and filling the second trench with asecond metallic material different from the first metallic material andplanarizing the second metallic material to form a second metallicstructure within the second trench.

According to still another aspect of the present disclosure, a method offorming an electrically programmable fuse (eFuse) is provided. Themethod includes: forming an integrated trench including a first trench,a second trench, and a third trench connected to the first and secondtrenches, wherein the first and second trenches have widths greater thana threshold distance and the third trench has a width not greater thanthe threshold distance in a dielectric layer located on a substrate;forming a blocking material layer in the first, second, and thirdtrenches; removing the blocking material layer from within the first andsecond trenches while the third trench is filled with a remainingportion of the blocking material layer; filling the first and secondtrenches with a first metallic material and planarizing the firstmetallic material to form a metallic anode within the first trench and ametallic cathode within the second trench; removing the remainingportion of the blocking material layer selective to the dielectricmaterial layer; and filling the third trench with a second metallicmaterial different from the first metallic material and planarizing thesecond metallic material to form a metallic fuselink within the secondtrench, wherein the metallic anode, the metallic cathode, and themetallic fuselink collectively constitute an eFuse.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the present disclosure, drawings that are labeled with the samenumeric label represent the same stage of a manufacturing process.Drawings that are labeled with the suffix “A” are top-down views.Drawings that are labeled with the suffix “B” are verticalcross-sectional views along a vertical plane B-B′ in the top-down viewlabeled with the same numeric label and the suffix “A.”

FIGS. 1A and 1B are views of an exemplary structure after formation of avia hole in a stack of a dielectric layer and a hard mask layeraccording to an embodiment of the present disclosure.

FIGS. 2A and 2B are views of the exemplary structure after formation ofline trenches in the stack of the dielectric layer and the dielectrichard mask layer according to an embodiment of the present disclosure.

FIGS. 3A and 3B are views of the exemplary structure after formation ofa blocking material layer according to an embodiment of the presentdisclosure.

FIGS. 4A and 4B are views of the exemplary structure after removal ofthe blocking material layer from within wide trenches while the blockingmaterial layer remains within narrow trenches according to an embodimentof the present disclosure.

FIGS. 5A and 5B are views of the exemplary structure after formation ofwide metallic structures according to an embodiment of the presentdisclosure.

FIGS. 6A and 6B are views of the exemplary structure after removal ofthe blocking material layer from within narrow trenches according to anembodiment of the present disclosure.

FIGS. 7A and 7B are views of the exemplary structure after formation ofnarrow metallic structures according to an embodiment of the presentdisclosure.

FIGS. 8A and 8B are views of the exemplary structure after formation ofan overlying dielectric layer and additional wide and narrow metallicstructures according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

As stated above, the present disclosure relates to size-filteredmultimetal structures in which metal lines having different widths havedifferent metallic compositions, an electrically programmable fuse(eFuse) employing a different material for a metallic fuselink than fora metallic anode and a metallic cathode, and methods of manufacturingthe same, which are now described in detail with accompanying figures.It is noted that like and corresponding elements mentioned herein andillustrated in the drawings are referred to by like reference numerals.

Referring to FIGS. 1A and 1B, an exemplary structure according to anembodiment of the present disclosure includes a substrate 10 and adielectric layer 20 formed thereupon. The substrate 10 can be asemiconductor substrate including at least one semiconductor device suchas a field effect transistor, or can be a combination of a semiconductorsubstrate and at least one metal interconnect structure. A metalinterconnect structure includes a dielectric material layer and a metalline structures that provide electrical conductive paths in horizontaldirections and metal via structures that provide electrically conductivepaths in vertical directions. The dielectric material layer includes adielectric material such as doped or undoped silicate glass, siliconnitride, silicon oxynitride, organosilicate glass (OGS), or acombination thereof.

The dielectric layer 20 is formed on the substrate 10 by deposition of adielectric material, which can be doped or undoped silicate glass,silicon nitride, silicon oxynitride, organosilicate glass (OGS), or acombination thereof. The dielectric layer 20 can be deposited, forexample, by chemical vapor deposition (CVD) or spin coating. Thethickness of the dielectric layer 20 can be from 20 nm to 1,000 nm,although lesser and greater thicknesses can also be employed.

A dielectric hard mask layer 30 can be optionally deposited on thedielectric layer 20. The dielectric hard mask layer 30 includes adielectric material having a greater resistance to abrasion than thedielectric material of the dielectric layer 20. The dielectric hard masklayer 30 can include, for example, silicon nitride layer or anorganosilicate-based dielectric material such as BLoK™ and NBLok™available from Applied Materials, Inc. and including silicon, carbon,oxygen, hydrogen, and optionally nitrogen. The dielectric hard masklayer 30 can be deposited, for example, by chemical vapor deposition(CVD). The thickness of the dielectric hard mask layer 30 can be from 2nm to 20 nm, although lesser and greater thicknesses can also beemployed.

A via cavity 18′ can be optionally formed in an upper portion of thedielectric layer 20. The via cavity 18′ can be formed, for example, byapplying a photoresist (not shown) on the top surface of the dielectriclayer 20 or on the top surface of the dielectric hard mask layer 30, ifpresent. The photoresist is subsequently lithographically exposed anddeveloped, and the remaining portion of the photoresist can be employedas a masking layer to etch exposed portions of the dielectric hard masklayer 10 and/or the exposed portions of the dielectric layer 20. Thephotoresist can be subsequently removed, for example, by ashing.

While an embodiment that employs a dielectric hard mask layer 30 in theexemplary structure is described herein, embodiments in which thedielectric hard mask layer 30 is omitted can also be employed.

Referring to FIGS. 2A and 2B, trenches are formed in the stack of thedielectric layer 20 and the dielectric hard mask layer 30. The trenchescan be line trenches. As used herein, a “line trench” refers to anytrench located in a line level of a metal interconnect structure. Thus,the line trenches of the present disclosure can be formed concurrentlywith other trenches (not shown) that can be employed to form metallines. The trenches may have a shape of a rectangle, a polygon, or anycurved shape in a top-down view.

As used herein, a “width” of a trench refers to a least dimensionbetween a pair of sidewalls that face the inside of the trench. Forexample, in a trench having a top-down shape of a rectangle, the widthis the lesser of the two separation distances measured between opposingpairs of sidewalls of the trench.

The trenches include two types of trenches. A trench of a first type hasa width that is greater than a lateral dimension. A trench of the firsttype is herein referred to as a “wide trench.” A trench of a second typehas a width that is equal to or less than the lateral dimension. Atrench of the second type is herein referred to as a “narrow trench.”The lateral dimension that distinguishes the first type of trenches andthe second type of trenches is herein referred to as a “thresholddistance.” The threshold distance can be, for example, from 20 nm to 500nm, although lesser and greater threshold distances can also beemployed.

The trenches can be formed by applying a photoresist (not shown) overthe dielectric hard mask layer 30, lithographically exposing anddeveloping the photoresist, and anisotropically etching the exposedportions of the dielectric hard mask layer 30 and underlying upperportions of the dielectric layer 20. The photoresist is subsequentlyremoved, for example, by ashing.

The trenches can include an integrated trench in which multiple types oftrenches are laterally adjoined to each other or one another. Forexample, an integrated trench can include a first trench 19A, a secondtrench 19B, and a third trench 19C connected to the first and secondtrenches (19A, 19B). The first and second trenches (19A, 19B) havewidths (e.g., w1 and w2, respectively) that are greater than thethreshold distance. The third trench 19C has a width, e.g., w3, that isnot greater than the threshold distance.

Further, the trenches can include a stand-alone second type trench 18,which is a trench of the second type that is not laterally adjoined toany trench of the first type. The stand-alone second type trench 18 caninclude a narrow trench line portion 18A and optionally at least oneunderlying narrow trench via portion 18B. In each of the narrow trenchline portion 18A and the at least one underlying narrow trench viaportion 18B, the width is not greater than the threshold distance, i.e.,narrower than a lateral separation distance corresponding to thethreshold distance. The at least one narrow trench via portion 18B canbe formed by vertically extending at least one via cavities 18′ that isformed at the processing step of FIGS. lA and 1B.

Still further, the trenches can include a stand-alone first type trench17, which is a trench of the first type that is not laterally adjoinedto any trench of the second type. The stand-alone first type trench 17can include a wide trench line portion (which coincides with thestand-alone first type trench 17 in FIGS. 2A and 2B) and optionally atleast one underlying wide trench via portion (not shown). In each of thewide trench line portion and the at least one underlying wide trench viaportion, the width is greater the threshold distance, i.e., wider than alateral separation distance corresponding to the threshold distance.

Referring to FIGS. 3A and 3B, a blocking material layer 40 is formed inthe trenches (17, 18, 19A, 19B, 19C). The blocking material layer 40includes a material that can be deposited conformally and is differentfrom the materials of the dielectric hard mask layer 30 and thedielectric layer 20. For example, the blocking material layer 40 caninclude a material selected from parylene, organosilicate glass, siliconoxide, silicon nitride, at least one elemental semiconductor material,at least one compound semiconductor material, and a combination thereof.

The blocking material layer 40 is deposited as a conformal layer, i.e.,a layer having substantially the same thicknesses at vertical portionsand at horizontal portions. The blocking material layer 40 can bedeposited, for example, by chemical vapor deposition (CVD) such asplasma enhanced chemical vapor deposition (PECVD) or low pressurechemical vapor deposition (LPCVD) or Atomic layer deposition (ALD).Depending on the conformity of the deposition process employed to formthe blocking material layer 40 and any taper, if present, of thesidewalls of the trenches (17, 18, 19A, 19B, 19C), a cavity 41 may beformed within one or more of the trenches of the second type (18, 19C)directly underneath a seam at which two portions of the blockingmaterial layer 40 make a lateral contact to seal off the cavity 41 ateach trench of the second type.

In order to seal off upper portions of the trenches of the second type(18, 19C), the blocking material layer 40 is deposited conformally witha thickness that is greater than one-half of the threshold distance. Thethickness of the blocking material layer 40 is selected to be less thanone-half of the minimum widths of the trenches of the first type (17,19A, 19B). Thus, the trenches of the first type do not include aseal-off region at which two portions of the blocking material layer 40make a lateral contact. Consequently, all surfaces of the trenches ofthe first type are spaced from the surfaces of the blocking materiallayer 40 by a distance that is equal to the thickness of thinness of theblocking material layer 40.

Referring to FIGS. 4A and 4B, portions of the blocking material layer 40are isotropically recessed by a thickness that is at least equal to thethickness of the blocking material layer 40 as measured at the trenchesof the first type (17, 19A, 19B). The amount of removal of the blockingmaterial layer 40 is limited so that the blocking material layer 40fills the trenches of the second type (18, 19C). Thus, the blockingmaterial layer 40 is removed from within the wide trenches, i.e.,trenches of the first type (17, 19A, 10B), and is not removed fromwithin the narrow trenches, i.e., trenches of the second type (18, 19C).

The surfaces of the trenches of the first type (17, 19A, 19B) arephysically exposed after the removal of the blocking material layer 40from within the trenches of the first type (17, 19A, 19B). However, thetrenches of the second type (18, 19C) are filled with the remainingportions of the blocking material layer 40. For example, the stand-alonesecond type trench 18 can be filled with a first blocking materialportion 40A, and the third trench 19C can be filled with a secondblocking material portion 40C. The first blocking material portion 40Aand the second blocking material portion 40C have widths that do notexceed the threshold distance.

The blocking material layer 40 is removed completely from within thetrenches of the first type (17, 19A, 19B) due to the ability of etchantsto isotropically etch the blocking material layer 40 and expose thesidewalls and bottom surfaces of the trenches of the first type (17,19A, 19B). Thus, all points on the sidewalls and bottom surfaces of thetrenches of the first type (17, 19A, 19B) are separated from the outersurfaces of the blocking material layer 40 by a distance that does notexceed the etch distance, i.e. the distance of the isotropic etchingduring the isotropic etch process. The etch distance is greater thanone-half of the threshold distance.

Referring to FIGS. 5A and 5B, metallic structures having a width greaterthan the threshold distance are formed by filling the trenches of thefirst type (17, 19A, 19B) with a first metallic material. Metallicstructures having a width greater than the threshold distance are hereinreferred to as “wide metallic structures.”

For example, the wide metallic structures can be formed in thestand-alone first type cavity 17, the first trench 19A, and the secondtrench 19B. Specifically, the stand-alone first type cavity 17, thefirst trench 19A, and the second trench 19B can be filled with a firstmetallic material and excess portions of the first metallic materialabove the top surface of the dielectric hard mask layer 30 can beremoved by planarization such as chemical mechanical planarization(CMP). The first metallic material can be any material that can beemployed in metal interconnect structure, and can include, but is notlimited to, copper, tungsten, aluminum, silver, gold, and alloysthereof. The top surface of the dielectric hard mask layer 30 can beemployed as a stopping layer during the planarization process. Inembodiments in which a dielectric hard mask layer 30 is not employed,the top surface of the dielectric layer 20 can be employed as a stoppinglayer.

The portions of the first metallic material in the stand-alone firsttype cavity 17, the first trench 19A, and the second trench 19B areherein referred to as a stand-alone first metallic material portion 57,an anode-side first metallic material portion 59A, and a cathode-sidefirst metallic material portion 59B, respectively. The topmost surfacesof the stand-alone first metallic material portion 57, the anode-sidefirst metallic material portion 59A, and the cathode-side first metallicmaterial portion 59B are coplanar with the top surface of the dielectrichard mask layer 30 if the dielectric hard mask layer 30 is present, andare coplanar with the topmost surface of the dielectric layer 20 if adielectric hard mask layer is not present.

Optionally, at least one first metallic liner can be formed within thetrenches of the first type (17, 19A, 19B). The at least one firstmetallic liner includes a first metallic liner material, which can be,but is not limited to, TiN, TaN, WN, TiC, TaC, WC, and combinationsthereof. The thickness of the at least one first metallic liner can befrom 2 nm to 20 nm, although lesser and greater thicknesses can also beemployed. If the at least one first metallic liner is employed, a firstmetallic liner material is deposited on exposed surfaces of thedielectric layer 20 within the trenches of the first type (17, 19A, 19B)and over the top surface of the dielectric layer 20 and the remainingportions of the blocking material layer 40 (such as the first blockingmaterial portion 40A and the second blocking material portion 40C) priorto deposition of the first metallic material described above. Portionsof the first metallic liner material formed above the top surface of thedielectric hard mask layer 30 are removed during the planarization ofthe first metallic material.

The remaining portions of the first metallic liner material in thetrenches of the first type (17, 19A, 19B) after the planarization of thefirst metallic material and the first metallic liner material constitutethe at least one first metallic liner. The portions of the firstmetallic liner material in the stand-alone first type cavity 17, thefirst trench 19A, and the second trench 19B are herein referred to as astand-alone first metallic liner 52, an anode-side first metallic liner54A, and a cathode-side first metallic liner 54B, respectively. Thetopmost surfaces of the stand-alone first metallic liner 52, theanode-side first metallic liner 54A, and the cathode-side first metallicliner 54B are coplanar with the top surface of the dielectric hard masklayer 30 if the dielectric hard mask layer 30 is present, and arecoplanar with the topmost surface of the dielectric layer 20 if adielectric hard mask layer is not present. The outer sidewalls andbottom surfaces of the stand-alone first metallic liner 52, theanode-side first metallic liner 54A, and the cathode-side first metallicliner 54B contact sidewalls and horizontal surfaces of the dielectriclayer 20. The inner sidewalls and top surfaces of the stand-alone firstmetallic liner 52, the anode-side first metallic liner 54A, and thecathode-side first metallic liner 54B contact sidewalls and horizontalsurfaces of the stand-alone first metallic material portion 57, theanode-side first metallic material portion 59A, and the cathode-sidefirst metallic material portion 59B, respectively.

If first metallic liners are present, each adjoined stack of a firstmetallic liner (52, 54B, 54C) and a first metallic material portion (57,59A, 59B) is herein referred to as a “first metallic structure.” Iffirst metallic liners are not present, each first metallic materialportion (57, 59A, 59B) is a first metallic structure.

Each first metallic structure (52, 54A, 54B, 57, 59A, 59B) is formed ina trench of the first type (17, 19A, 19B), from which the blockingmaterial layer 40 is removed completely due to the ability of etchantsto isotropically etch the blocking material layer 40. Thus, each firstmetallic structure (52, 54A, 54B, 57, 59A, 59B) includes at least onepoint located at a distance of more than one half of the thresholddistance from any outer sidewall surface of that metallic structure.

Referring to FIGS. 6A and 6B, the blocking material layer 40 is removedfrom within trenches of the second type (18, 19C), i.e., the narrowtrenches, by an etch, which can be an isotropic etch or an anisotropicetch. An etch chemistry that removes the material of the blockingmaterial layer 40 selectively to the materials of the first metallicstructure (52, 54A, 54B, 57, 59A, 59B) and the dielectric layer 20 canbe employed. Remaining portions of the blocking material layer 40 can beremoved by this etch. Sidewall surfaces and bottom surfaces of thetrenches of the second type (18, 19C).

Referring to FIGS. 7A and 7B, metallic structures having a width lessthan the threshold distance are formed by filling the trenches of thesecond type (18, 19C) with a second metallic material. Metallicstructures having a width less than the threshold distance are hereinreferred to as “narrow metallic structures.”

For example, the narrow metallic structures can be formed in thestand-alone second type cavity 18 and the third cavity 19C.Specifically, the stand-alone second type cavity 18 and the third trench19C can be filled with a second metallic material and excess portions ofthe second metallic material above the top surface of the dielectrichard mask layer 30 can be removed by planarization such as chemicalmechanical planarization (CMP). The second metallic material can be anymaterial that can be employed in metal interconnect structure, and caninclude, but is not limited to, copper, tungsten, aluminum, silver,gold, and alloys thereof. The second metallic material can be the sameas, or can be different from, the first metallic material. The topsurface of the dielectric hard mask layer 30 can be employed as astopping layer during the planarization process. In embodiments in whicha dielectric hard mask layer 30 is not employed, the top surface of thedielectric layer 20 can be employed as a stopping layer.

The portions of the second metallic material in the stand-alone secondtype cavity 18 and the third trench 19C are herein referred to as astand-alone second metallic material portion 68 and a fuselink secondmetallic material portion 69, respectively. The topmost surfaces of thestand-alone second metallic material portion 68 and the fuselink secondmetallic material portion 69 are coplanar with the top surface of thedielectric hard mask layer 30 if the dielectric hard mask layer 30 ispresent, and are coplanar with the topmost surface of the dielectriclayer 20 if a dielectric hard mask layer is not present.

In one embodiment, the second metallic material is different from thefirst metallic material. Further, the first metallic material and thesecond metallic material can be selected so that the first metallicmaterial has greater resistance to electromigration than the secondmetallic material.

Optionally, at least one second metallic liner can be formed within thetrenches of the second type (18, 19C). The at least one second metallicliner includes a second metallic liner material, which can be, but isnot limited to, TiN, TaN, WN, TiC, TaC, WC, and combinations thereof.The thickness of the at least one second metallic liner can be from 2 nmto 20 nm, although lesser and greater thicknesses can also be employed.If the at least one second metallic liner is employed, a second metallicliner material is deposited on exposed surfaces of the dielectric layer20 within the trenches of the second type (18, 19C) and over the topsurface of the dielectric layer 20 and the first metallic structures(52, 54A, 54B, 57, 59A, 59B) prior to deposition of the second metallicmaterial described above. Portions of the second metallic liner materialformed above the top surface of the dielectric hard mask layer 30 areremoved during the planarization of the second metallic material.

The remaining portions of the second metallic liner material in thetrenches of the second type (18, 19C) after the planarization of thesecond metallic material and the second metallic liner materialconstitute the at least one second metallic liner. The portions of thesecond metallic liner material in the stand-alone second type cavity 18and the third cavity 19C are herein referred to as a stand-alone secondmetallic liner 63 and a fuselink second metallic liner 64, respectively.The topmost surfaces of the stand-alone second metallic liner 63 and thefuselink second metallic liner 64 are coplanar with the top surface ofthe dielectric hard mask layer 30 if the dielectric hard mask layer 30is present, and are coplanar with the topmost surface of the dielectriclayer 20 if a dielectric hard mask layer is not present. The outersidewalls and bottom surfaces of the stand-alone second metallic liner63 and the fuselink second metallic liner 64 contact sidewalls andhorizontal surfaces of the dielectric layer 20. The inner sidewalls andtop surfaces of the stand-alone second metallic liner 63 and thefuselink second metallic liner 64 contact sidewalls and horizontalsurfaces of the stand-alone second metallic material portion 68 and thefuselink second metallic material portion 69, respectively.

The first metallic structures (52, 54A, 54B, 57, 59A, 59B) and thesecond metallic structures (63, 64, 68, 69) have top surfaces that arecoplanar with each other and with the top surface of the dielectric hardmask layer 30 if the dielectric hard mask layer 30 is present, or withthe topmost surface of the dielectric layer 20 if a dielectric hard masklayer is not present.

If second metallic liners are present, each adjoined stack of a secondmetallic liner (63, 64) and a second metallic material portion (68, 69)is herein referred to as a “second metallic structure.” If secondmetallic liners are not present, each second metallic material portion(68, 69) is a second metallic structure.

If at least one first metallic liner (52, 54A, 54B) and at least onesecond metallic liner (63, 64) are employed, the second metallicmaterial can be the same as, or can be different from, the firstmetallic material. Further, the thickness of the at least one secondmetallic liner (63, 64) can be the same as, or can be different from,the thickness of the at least one first metallic liner (52, 54A, 54B).

Each second metallic structure (63, 64, 68, 69) is formed in a trench ofthe second type (18, 19C), in which portions of the blocking materiallayer 40 are present at the processing step of FIGS. 4A and 4B due tothe inability of etchants to reach the inside of the trenches of thesecond type (18, 19C). Thus, for each point within the second metallicstructures (63, 64, 68, 69), a minimum distance to outer sidewallsurfaces of the second metallic structure (63, 64, 68, or 69) is notgreater than one half of the threshold distance.

The various metallic structures (52, 54A, 54B, 57, 59A, 59B, 63, 64, 68,69) can be combined to form a device structure. For example, thecombination of the metallic structures within the integrated trench(19A, 19B, 19C) can be employed as an electrically programmable fuse(eFuse), which includes the optional anode-side first metallic liner54A, the anode-side first metallic material portion 59A, the optionalcathode-side first metallic liner 54B, the cathode-side first metallicmaterial portion 59B, the optional fuselink second metallic liner 64,and the fuselink second metallic material portion 69. The combination ofthe anode-side first metallic liner 54A and the anode-side firstmetallic material portion 59A or the anode-side first metallic materialportion 59A alone (if an anode-side first metallic liner 54A is notemployed) constitutes a metallic anode (54A, 59A). The combination ofthe cathode-side first metallic liner 54B and the cathode-side firstmetallic material portion 59B or the cathode-side first metallic liner54B alone (if a cathode-side first metallic liner 54B is not employed)constitutes a metallic cathode (54B, 59B). The combination of thefuselink second metallic liner 64 and the fuselink second metallicmaterial portion 69 or the fuselink second metallic material portion 69alone (if a fuselink second metallic liner is not employed) constitutesa metallic fuselink (64, 69). The topmost surfaces of the metallicfuselink (64, 69), the metallic anode (54A, 59A), and the metalliccathode (54B, 59B) are coplanar.

The metallic anode (54A, 59A) includes at least one point located at adistance of more than one half of the threshold distance from any outersidewall surface of the metallic anode (54A, 59A) that contact thesidewalls of the first trench 19A, and the metallic cathode (54B, 59B)includes at least one point located at a distance of more than one halfof the threshold distance from any outer sidewall surface of themetallic cathode (54B, 59B) that contact the sidewalls of the secondtrench 19B. For each point within the metallic fuselink (64, 69), aminimum distance to outer sidewall surfaces of the metallic fuselink(64, 69) is not greater than one half of the threshold distance.

In one embodiment, the first metallic material, which is present in theanode-side first metallic material portion 59A and the cathode-sidefirst metallic material portion 59B, can have greater resistance toelectromigration than the second metallic material, which is present inthe fuselink second metallic material portion 69. In this case, thegreater resistance to electromigration of the material of the anode-sidefirst metallic material portion 59A and the cathode-side first metallicmaterial portion 59B relative to the material of the fuselink secondmetallic material portion 69 can confine the electromigration within theelectrically programmable fuse within the cathode-side first metallicmaterial portion 59B.

Referring to FIGS. 8A and 8B, an overlying dielectric layer 120 and anoverlying dielectric hard mask layer 130 can be deposited over theexemplary structure shown in FIGS. 7A and 7B. The same processingmethods of FIGS. 1A-7B can be employed at the level of the overlyingdielectric layer 120 and the overlying dielectric hard mask layer 130 toform additional narrow metallic structures and additional wide metallicstructures, which are embedded in the stack of the overlying dielectriclayer 120 and the overlying dielectric hard mask layer 130. For example,each overlying wide metallic structure can include a first overlyingmetallic material portion 157 and a first overlying metallic liner 152,each of which includes a first metallic material and a first metallicliner material, respectively. Each overlying narrow metallic structurecan include a second overlying metallic material portion 168 and asecond overlying metallic liner 163, each of which includes a secondmetallic material and a second metallic liner material, respectively.

While the disclosure has been described in terms of specificembodiments, it is evident in view of the foregoing description thatnumerous alternatives, modifications and variations will be apparent tothose skilled in the art. For example, though the present disclosure isdescribed with exemplary structures including a field effect transistorand an antifuse structure, the present disclosure may be practicedwithout any field effect transistor. Accordingly, the disclosure isintended to encompass all such alternatives, modifications andvariations which fall within the scope and spirit of the disclosure andthe following claims.

1. A structure comprising: a dielectric layer located on a substrate; afirst metallic structure comprising a first metallic portion including afirst metallic material and embedded in said dielectric layer; and asecond metallic structure comprising a second metallic portion includinga second metallic material different from said first metallic materialand embedded in said dielectric layer.
 2. The structure of claim 1,wherein a topmost surface of said first metal structure is coplanar witha topmost surface of said second metal structure.
 3. The structure ofclaim 1, wherein said first metallic structure further comprises atleast one first metallic liner having first outer sidewalls contactingsaid dielectric layer and first inner sidewalls contacting said firstmetallic portion, and said second metallic structure further comprisesat least one second metallic liner having second outer sidewallscontacting said dielectric layer and second inner sidewalls contactingsaid second metallic portion.
 4. The structure of claim 1, wherein asidewall of said first metallic structure is in direct contact with asidewall of said second metallic structure.
 5. The structure of claim 1,wherein, for each point within said second metallic structure, a minimumdistance to outer sidewall surfaces of said second metallic structure isnot greater than one half of a threshold distance, and said firstmetallic structure includes at least one point located at a distance ofmore than one half of said threshold distance from any outer sidewallsurface of said first metallic structure.
 6. A structure comprising anelectrically programmable fuse (eFuse), wherein said eFuse is embeddedin a dielectric layer located on a substrate and comprises an assemblyof a metallic anode, a metallic fuselink, and a metallic cathode, saidmetallic anode comprises a first metallic portion including a firstmetallic material, and said metallic cathode comprises a second metallicportion including said first metallic material, and said metallicfuselink contacts said metallic anode and said metallic cathode andcomprises a third metallic portion including a second metallic materialdifferent from said first metallic material.
 7. The structure of claim6, wherein topmost surfaces of said metallic fuselink, said metallicanode, and said metallic cathode are coplanar.
 8. The structure of claim6, wherein said metallic anode further comprises at least one firstmetallic liner having first outer sidewalls contacting said dielectriclayer and first inner sidewalls contacting said first metallic portion,said metallic cathode further comprises at least one second metallicliner having second outer sidewalls contacting said dielectric layer andsecond inner sidewalls contacting said second metallic portion, and saidmetallic fuselink further comprises at least one third metallic linerhaving third outer sidewalls contacting said dielectric layer and thirdinner sidewalls contacting said third metallic portion.
 9. The structureof claim 6, wherein said first metallic material has greater resistanceto electromigration than said second metallic material.
 10. Thestructure of claim 6, wherein, for each point within said metallicfuselink, a minimum distance to outer sidewall surfaces of said metallicfuselink is not greater than one half of a threshold distance, saidmetallic anode includes at least one point located at a distance of morethan one half of said threshold distance from any outer sidewall surfaceof said metallic anode, and said metallic cathode includes at least onepoint located at a distance of more than one half of said thresholddistance from any outer sidewall surface of said metallic cathode.
 11. Amethod of forming a structure, said method comprising: forming a firsttrench having a width greater than a threshold distance and a secondtrench having a width not greater than said threshold distance in adielectric layer located on a substrate; forming a blocking materiallayer in said first trench and said second trench; removing saidblocking material layer from within said first trench while said secondtrench is filled with a remaining portion of said blocking materiallayer; filling said first trench with a first metallic material andplanarizing said first metallic material to form a first metallicstructure within said first trench; removing said remaining portion ofsaid blocking material layer selective to said dielectric materiallayer; and filling said second trench with a second metallic materialdifferent from said first metallic material and planarizing said secondmetallic material to form a second metallic structure within said secondtrench.
 12. The method of claim 11, wherein a top surface of said secondmetallic structure is coplanar with a top surface of said first metallicstructure after planarization of said second metallic material.
 13. Themethod of claim 11, wherein said blocking material layer is depositedconformally with a thickness that is greater than one half of saidthreshold distance.
 14. The method of claim 11, wherein a dielectrichard mask layer having a greater resistance to abrasion than saiddielectric layer is deposited on said dielectric layer prior toformation of said first and second trenches, and said first metallicmaterial and said second metallic material are planarized employing saiddielectric hard mask layer as a stopping layer.
 15. The method of claim11, wherein said blocking material layer includes a material selectedfrom parylene, organosilicate glass, silicon oxide, silicon nitride, atleast one elemental semiconductor material, and at least one compoundsemiconductor material.
 16. A method of forming an electricallyprogrammable fuse (eFuse), said method comprising: forming an integratedtrench including a first trench, a second trench, and a third trenchconnected to said first and second trenches, wherein said first andsecond trenches have widths greater than a threshold distance and saidthird trench has a width not greater than said threshold distance in adielectric layer located on a substrate; forming a blocking materiallayer in said first, second, and third trenches; removing said blockingmaterial layer from within said first and second trenches while saidthird trench is filled with a remaining portion of said blockingmaterial layer; filling said first and second trenches with a firstmetallic material and planarizing said first metallic material to form ametallic anode within said first trench and a metallic cathode withinsaid second trench; removing said remaining portion of said blockingmaterial layer selective to said dielectric material layer; and fillingsaid third trench with a second metallic material different from saidfirst metallic material and planarizing said second metallic material toform a metallic fuselink within said second trench, wherein saidmetallic anode, said metallic cathode, and said metallic fuselinkcollectively constitute an eFuse.
 17. The method of claim 16, wherein atop surface of said metallic fuselink is coplanar with top surfaces ofsaid metallic anode and said metallic cathode after planarization ofsaid second metallic material.
 18. The method of claim 16, wherein saidblocking material layer is deposited conformally with a thickness thatis greater than one half of said threshold distance.
 19. The method ofclaim 16, wherein a dielectric hard mask layer having a greaterresistance to abrasion than said dielectric layer is deposited on saiddielectric layer prior to formation of said first, second, and thirdtrenches, and said first metallic material and said second metallicmaterial are planarized employing said dielectric hard mask layer as astopping layer.
 20. The method of claim 16, wherein said blockingmaterial layer includes a material selected from parylene,organosilicate glass, silicon oxide, silicon nitride, at least oneelemental semiconductor material, and at least one compoundsemiconductor material.